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PE4246
Product Specification
Figure 3. Pin Configuration
Device Description
The PE4246 high-isolation SPST RF Switch is
V DD
1
6
RF2
designed to support a variety of applications
where high isolation performance is demanded
GND
RF1
2
3
Exposed
Solder Pad
(bottom side)
5
4
GND
CTRL
and a non-reflective input and output is desired.
This switch is able to replace multiple lesser
performing switches in a very small 3x3 mm DFN
footprint.
Table 4. Operating Ranges
Parameter
Min
Typ
Max
Unit
Table 2. Pin Descriptions
V DD Power Supply
2.7
3.0
3.3
V
Pin
No.
1
2
3
Pin
Name
V DD
GND
RF1
Description
Nominal 3 V supply connection. 1
Ground connection. 3
RF port . 2
CMOS or TTL logic level:
I DD Power Supply Current
(V DD = 3 V, V CNTL = 3 V)
T OP Operating temperature
Control Voltage High
Control Voltage Low
-40
0.7xV DD
0
33
40
85
5
0.3xV DD
μA
°C
V
V
4
CTRL
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
Table 5. Control Logic Truth Table
5
6
GND
RF2
Ground connection . 3
RF port . 2
Control Voltage
CTRL = CMOS or TTL High
Signal Path
RF1 to RF2
Notes: 1. A bypass capacitor should be placed as close as possible
to the pin.
CTRL = CMOS or TTL Low
RF1 isolated from RF2
2. Both RF pins must be DC blocked by an external capacitor
or held at 0 V DC .
3. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Control Logic
The control logic input pin (CTRL) is typically driven by
a 3-volt CMOS logic level signal, and has a threshold of
50% of V DD . For flexibility to support systems that have
Symbol
V DD
V I
T ST
P IN
V ESD
Parameter/Condition
Power supply voltage
Voltage on CTRL input
Storage temperature
Input power (50 ? ),
CTRL=1/CTRL=0
ESD voltage
(Human Body Model)
Min
-0.3
-0.3
-65
Max
4.0
5.5
150
33/24
200
Unit
V
V
°C
dBm
V
5-volt control logic drivers, the control logic input has
been designed to handle a 5-volt logic HIGH signal. (A
minimal current will be sourced out of the V DD pin when
the control logic input voltage level exceeds V DD .)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE4246 in
the 6-lead 3x3 DFN package is MSL1.
?2003-2010 Peregrine Semiconductor Corp. All rights reserved.
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS? de-
vices are immune to latch-up.
Document No. 70-0090-09 │ UltraCMOS? RFIC Solutions
Page 2 of 8
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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